Manufacture of semiconductor device and wafer used therefor



(57)【要約】 【目的】 シリコン活性層を研磨する工程での研磨膜厚 の測定を容易にする。 【構成】 シリコン(100)面である、ウェハ1の主 表面1aを研磨する前に、平面視略正方形状でかつその 所定辺が結晶方位<110>と略平行である開口7a〜 7dを備えた、断面視略V字型の凹部6a〜6dを、開 口の大きさを違えて複数種類、主表面1aに異方性エッ チングによって形成し、研磨工程後に、凹部6a〜6d の、残存または消失を確認する。 【効果】 膜厚測定箇所の変動、または、研磨によるウ ェハの反りの影響を受けずに、容易にシリコン活性層4 の研磨膜厚を求めることができ、品質の安定化、歩留り 向上が図れる。
PURPOSE: To easily measure a depth of abrasion in a polishing process where a silicon active layer is ground. CONSTITUTION: Recesses 6a to 6d nearly V-shaped cross-sectionally and having openings 7a to 7d which are square in plan view and different from each other in size and whose prescribed sides are nearly parallel with a crystal orientation <110> are provided to a silicon wafer 1 by anisotropic etching before the main surface 1a of (100) plane of the silicon wafer 1 is ground, and it is confirmed that the recesses 6a to 6d are left unremoved or erased out after a polishing process is finished. By this setup, a depth of abrasion of a silicon active layer 4 is easily obtained without being affected by the change of abrasion depth measuring spot and the warpage of a wafer due to grinding, so that wafers are capable of being improved in yield. COPYRIGHT: (C)1996,JPO




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Cited By (5)

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    JP-2012064847-AMarch 29, 2012Lapis Semiconductor Co Ltd, ラピスセミコンダクタ株式会社半導体装置の製造方法
    JP-4719991-B2July 06, 2011株式会社デンソー炭化珪素半導体装置の製造方法
    US-7141506-B2November 28, 2006Sharp Kabushiki Kaisha, Fujio MasuokaMethod for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same
    US-8282196-B2October 09, 2012Samsung Electronics Co., Ltd.Micro electro mechanical system device and method of manufacturing the same